A field programmable gate array (FPGA; programmable logic circuit) has been known as a device that may electrically change a circuit design of a digital circuit. The FPGA is a large scale integration circuit (LSI) including a plurality of logic gates. The FPGA serves as a predetermined logic circuit by writing a configuration data describing a logic relationship and a connection relationship between the logic gates in a configuration random access memory (RAM) included in the FPGA.
A circuit design may be mounted within a shorter period of time than in the case of manufacturing circuit components depending on a design, by using the FPGA in circuit components of various electronic devices.
Further, the FPGA may change the configuration data to easily change the circuit design without changing hardware and therefore has been used in various products in addition to electronic devices. The FPGA has also been used for a channel adapter (CA) that is mounted in a storage control apparatus for instance.
Meanwhile, in the FPGA, errors may occur in the configuration RAM. As the errors occurring in the configuration RAM, there are a “hard error” that damages a circuit itself and a “soft error” that destructs data within a RAM due to radiation, such as cosmic rays.
When the “hard error” occurs in the configuration RAM, there is a need to exchange the FPGA itself, but when the “soft error” occurs, the FPGA may be reconfigured to be recovered.
For example, in the storage device using the FPGA in the CA, when the soft error occurs in the FPGA of the CA, the CA is hard reset to be rebooted, and thus the FPGA is recovered from the soft error state.
FIGS. 7A and 7B are diagrams illustrating processing at the time of the occurrence of the soft error of the FPGA in the storage control apparatus according to the related art and FIG. 8 is a sequence diagram of the processing.
As illustrated in FIG. 7A, in a storage system 1000 including a host 1010 and a storage device 1020, in a CA 1021 of the storage device 1020, processing according to the related art when a soft error is detected in the FPGA will be described. Note that, in FIGS. 7B and 8, reference numerals with parentheses represent corresponding processing.
The storage device 1020 includes the CA 1021, a controller module (CM) 1022 and the CA 1021 is connected with a channel (CH) 1012 of the host 1010. The CH 1012 is, for example, a fibre channel interface. In the example illustrated in FIGS. 7 and 8, the host 1010 is connected with the storage device 1020 by an optical fibre cable.
When the soft error of the FPGA is detected, first, (1) the hard reset is performed in the CA 1021 and a power supply of the CA 1021 is interrupted. By doing so, (2) the host 1010 is disconnected with the storage device 1020 and in the CH 1012 of the host 1010, a communication disconnection (light interruption) between the host 1010 and the storage device 1020 is detected.
In an operating system (OS) 1011 of the host 1010, (3) a path disconnection between the host 1010 and the storage device 1020 is recognized based on the detection of the light interruption of the CH 1012.
The CM 1022 (4) determines a failure of the CA 1021 since the CA 1021 is hard reset, sets the CA 1021 to an unusable state, and outputs a failure notification. By receiving the failure notification, a repair and maintenance customer engineer (CE) of an apparatus is dispatched to, for example, perform a board exchange operation of the CA 1021.
The CM 1022 (5) reboots (restarts) the CA 1021 and incorporates the CA 1021. Subsequently, (6) an operator operates the host 1010 to perform path online processing, such that the path between the host 1010 and the storage device 1020 is recovered and the storage system 1000 is in a usable state.
According to the conventional method of recovering from soft error of FPGA, the path between the host 1010 and the CA 1021 is disabled during the time period from the recognition (3) of the path disconnection between the host 1010 and the storage device 1020 to the path online processing (6).
[Patent Literature 1] Japanese Laid-open Patent Publication No. 2012-14353
However, in the storage system according to the related art, in order to recover the path between the host 1010 and the storage device 1020, an operator needs to perform the pass online processing operation after completion of CA reboot (see reference numeral (5)). Therefore, there is a problem in that the recovery of the storage system 1000 may not be performed rapidly and is complicated.
Further, as described above, when the failure of the CA 1021 is determined, and thus the failure notification (see reference numeral (4)) is performed by the CM 1022, there is a case in which the repair and maintenance customer engineer of the apparatus is dispatched when the failure notification is issued and the board exchange operation of the CA 1021 is performed. However, since the soft error of the FPGA does not incur the abnormality of hardware of the FPGA, the board exchange operation is unnecessary and inefficient.